![]() And I may be able to adjust the code shown in the Abacus project by changing the "repeat(13)" to "repeat(N-3)" and then also varying the bit positions. I can code up, easily, anything I want where I already know the value of N, a priori. This happens on every transition from (N mod 3=0) to (N mod 3=1) boundary. ![]() (The reason has to do with the number of "S3" outputs, which cannot exceed 3 in the higher order bits - words are difficult here but the pictures illustrate better.) Then when going from 9-bit binary to 10-bit binary, another transition takes place. At that point, transitioning to 7-bit, a new layer is required in the tree. Once 4-bit binary is reached, the first dabble module is required. Note that with up to N=3, there's no need for a "dabble" module block. One image: 7400-series implementation of the double-dabble block showing it is combinatorial (as is everything here) - this is implemented with a verilog "if/else" mapped through LUTs that I already know how to do and do not need any help achieving. It's the point of this question, in fact.) (I do not know how to implement generic tree structures in verilog, just yet. I am curious about how the compiler optimizes it and would like to compare those results with ones I hope to implement in tree-form, once I learn how to do that in verilog. I already know how to do this and I do not need any help with it. One image: what I already know how to do for a "24-bit binary to BCD", which sets up a 49-bit array (input and output) to achieve it. (I want to know how to write this in verilog as a generic, parameterized module.) One image: phase 2 verilog module, with backward-pruning, to implement a "24-bit binary to 29-bit BCD" case. One image: phase 1 verilog module to implement a "24-bit binary to 31-bit BCD" case. Two images: one for "9-bit binary to 11-bit BCD" and other for "10-bit binary to 13-bit BCD", which illustrates yet another transition in the tree structure. Two images: one for "6-bit binary to 7-bit BCD" and another for "7-bit binary to 9-bit BCD", which illustrates one transition in the tree structure. I've included a diagram illustrating the following cases: Let me first illustrate a few concrete examples to help get across the larger question I have with respect to verilog. It's based upon the dabble algorithm (easily looked up on Wiki.) I'm currently intending to modify some existing verilog code (the Abacus project at Digilent - thanks for that.) In particular, the code that converts binary to BCD. (I had unending troubles using the Xilinx Installer to get 2020.1, so gave up - though just today I downloaded it using a link their forum person provided plus WGET. I've just downloaded 2017.4 (with update 1) and installed it, successfully. If not, I'll try to improve it based upon comments I receive. I hope the following is sufficiently clear. I also have only just started at this forum site and have only read a small number of posts here. ![]() ![]() (I enjoyed the language experiences but hated the crappy floor planning tool and so floor-planned out everything by hand, instead, with far far better success that way.) ![]() My last project was a few self-tutorials on the Xilinx 4000 series part, to date myself a bit. My modest background has been with VHDL, but it dates back to the early 2000's and I've been away from any HDL for more than 15 years. ![]()
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